DS2155 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2155

T1/E1/J1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

DS2155

Figure 35-23. Transmit IBO Frame Interleave Mode Timing ..................................................................................223

Figure 37-1. Intel Multiplexed Bus Read Timing (BTS = 0/MUX = 1)...................................................................227

Figure 37-2. Intel Multiplexed Bus Write Timing (BTS = 0/MUX = 1)..................................................................227

Figure 37-3. Motorola Multiplexed Bus Timing (BTS = 1/MUX = 1) ....................................................................228

Figure 37-4. Intel Nonmultiplexed Bus Read Timing (BTS = 0/MUX = 0) ............................................................230

Figure 37-5. Intel Nonmultiplexed Bus Write Timing (BTS = 0/MUX = 0) ...........................................................230

Figure 37-6. Motorola Nonmultiplexed Bus Read Timing (BTS = 1/MUX = 0).....................................................231

Figure 37-7. Motorola Nonmultiplexed Bus Write Timing (BTS = 1/MUX = 0)....................................................231

Figure 37-8. Receive-Side Timing ...........................................................................................................................233

Figure 37-9. Receive-Side Timing, Elastic Store Enabled .......................................................................................234

Figure 37-10. Receive Line Interface Timing ..........................................................................................................234

Figure 37-11 Receive Timing Delay RCLK to BPCLK..........................................................................................235

Figure 37-12. Transmit-Side Timing........................................................................................................................237

Figure 37-13. Transmit-Side Timing, Elastic Store Enabled....................................................................................238

Figure 37-14. Transmit Line Interface Timing.........................................................................................................238

1.2 Table of Tables

Table 4-A. Pin Description Sorted by Pin Number ....................................................................................................32

Table 5-A. Register Map Sorted by Address..............................................................................................................35

Table 9-A. T1 Alarm Criteria .....................................................................................................................................56

Table 10-A. E1 Sync/Resync Criteria ........................................................................................................................58

Table 10-B. E1 Alarm Criteria ...................................................................................................................................63

Table 14-A. T1 Line Code Violation Counting Options ............................................................................................78

Table 14-B. E1 Line-Code Violation Counting Options ............................................................................................78

Table 14-C. T1 Path Code Violation Counting Arrangements...................................................................................80

Table 14-D. T1 Frames Out-of-Sync Counting Arrangements ..................................................................................81

Table 16-A. Time Slot Numbering Schemes..............................................................................................................92

Table 17-A. Idle-Code Array Address Mapping ........................................................................................................98

Table 17-B. GRIC and GTIC Functions...................................................................................................................100

Table 19-A. Elastic Store Delay After Initialization ................................................................................................110

Table 23-A. HDLC Controller Registers..................................................................................................................129

Table 24-A. Transformer Specifications ..................................................................................................................160

Table 27-A. Transmit Error-Insertion Setup Sequence ............................................................................................182

Table 27-B. Error Insertion Examples......................................................................................................................184

Table 34-A. Instruction Codes for IEEE 1149.1 Architecture .................................................................................205

Table 34-B. ID Code Structure.................................................................................................................................206

Table 34-C. Device ID Codes...................................................................................................................................206

Table 34-D. Boundary Scan Control Bits.................................................................................................................207

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