DS2155 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2155

T1/E1/J1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

DS2155

1.1 Table of Figures

Figure 3-1. Block Diagram.........................................................................................................................................15

Figure 3-2. Receive and Transmit LIU.......................................................................................................................16

Figure 3-3. Receive and Transmit Framer/HDLC......................................................................................................17

Figure 3-4. Backplane Interface .................................................................................................................................18

Figure 4-1. 10mm CSBGA Pin Configuration ...........................................................................................................34

Figure 6-1. Programming Sequence ...........................................................................................................................41

Figure 8-1. Clock Map................................................................................................................................................47

Figure 16-1. Simplified Diagram of Receive Signaling Path .....................................................................................85

Figure 16-2. Simplified Diagram of Transmit Signaling Path....................................................................................91

Figure 20-1. CRC-4 Recalculate Method .................................................................................................................111

Figure 24-1. Typical Monitor Application ...............................................................................................................146

Figure 24-2. CMI Coding .........................................................................................................................................148

Figure 24-3. Basic Interface .....................................................................................................................................158

Figure 24-4. Protected Interface Using Internal Receive Termination.....................................................................159

Figure 24-5. E1 Transmit Pulse Template................................................................................................................161

Figure 24-6. T1 Transmit Pulse Template................................................................................................................161

Figure 24-7. Jitter Tolerance ....................................................................................................................................162

Figure 24-8. Jitter Tolerance (E1 Mode) ..................................................................................................................162

Figure 24-9. Jitter Attenuation (T1 Mode) ...............................................................................................................163

Figure 24-10. Jitter Attenuation (E1 Mode) .............................................................................................................163

Figure 24-11. Optional Crystal Connections ............................................................................................................164

Figure 26-1. Simplified Diagram of BERT in Network Direction ...........................................................................173

Figure 26-2. Simplified Diagram of BERT in Backplane Direction ........................................................................173

Figure 28-1. IBO Example .......................................................................................................................................188

Figure 29-1. ESIB Group of Four DS2155s .............................................................................................................189

Figure 33-1 T1 Transmit Flow Chart.......................................................................................................................196

Figure 33-2 E1 Transmit Flow Chart.......................................................................................................................198

Figure 34-1. JTAG Functional Block Diagram ........................................................................................................201

Figure 34-2. TAP Controller State Diagram.............................................................................................................204

Figure 35-1. Receive-Side D4 Timing......................................................................................................................210

Figure 35-2. Receive-Side ESF Timing....................................................................................................................210

Figure 35-3. Receive-Side Boundary Timing (Elastic Store Disabled)....................................................................211

Figure 35-4. Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)...................................................211

Figure 35-5. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)...................................................212

Figure 35-6. Transmit-Side D4 Timing ....................................................................................................................212

Figure 35-7. Transmit-Side ESF Timing ..................................................................................................................213

Figure 35-8. Transmit-Side Boundary Timing (with Elastic Store Disabled) ..........................................................213

Figure 35-9. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) .................................................214

Figure 35-10. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ...............................................214

Figure 35-11. Receive-Side Timing .........................................................................................................................215

Figure 35-12. Receive-Side Boundary Timing (with Elastic Store Disabled)..........................................................215

Figure 35-13. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (Elastic Store Enabled) .........................216

Figure 35-14. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (Elastic Store Enabled) .........................216

Figure 35-15. Receive IBO Channel Interleave Mode Timing ................................................................................217

Figure 35-16. Receive IBO Frame Interleave Mode Timing....................................................................................218

Figure 35-17. G.802 Timing, E1 Mode Only ...........................................................................................................219

Figure 35-18. Transmit-Side Timing........................................................................................................................219

Figure 35-19. Transmit-Side Boundary Timing (Elastic Store Disabled) ................................................................220

Figure 35-20. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled) .......................220

Figure 35-21. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled) ........................221

Figure 35-22. Transmit IBO Channel Interleave Mode Timing...............................................................................222

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