DS2155 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

Номер в каталоге

Компоненты Описание

производитель

DS2155

T1/E1/J1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

DS2155

28.1 CHANNEL INTERLEAVE .........................................................................................................................186

28.2 FRAME INTERLEAVE..............................................................................................................................186

29. EXTENDED SYSTEM INFORMATION BUS (ESIB) .......................................................................189

30. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER ........................................................193

31. FRACTIONAL T1/E1 SUPPORT .........................................................................................................193

32. USER-PROGRAMMABLE OUTPUT PINS........................................................................................195

33. TRANSMIT FLOW CHARTS...............................................................................................................196

34. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .................................201

34.1 DESCRIPTION .........................................................................................................................................201

34.2 INSTRUCTION REGISTER........................................................................................................................204

34.3 TEST REGISTERS....................................................................................................................................206

34.4 BOUNDARY SCAN REGISTER .................................................................................................................206

34.5 BYPASS REGISTER .................................................................................................................................206

34.6 IDENTIFICATION REGISTER ...................................................................................................................206

35. FUNCTIONAL TIMING DIAGRAMS.................................................................................................210

35.1 T1 MODE ...............................................................................................................................................210

35.2 E1 MODE ...............................................................................................................................................215

36. OPERATING PARAMETERS ..............................................................................................................224

37. AC TIMING PARAMETERS AND DIAGRAMS ...............................................................................226

37.1 MULTIPLEXED BUS AC CHARACTERISTICS ..........................................................................................226

37.2 NONMULTIPLEXED BUS AC CHARACTERISTICS ...................................................................................229

37.3 RECEIVE-SIDE AC CHARACTERISTICS ..................................................................................................232

37.4 BACKPLANE CLOCK TIMING: AC CHARACTERISTICS .........................................................................235

37.5 TRANSMIT AC CHARACTERISTICS ........................................................................................................236

38. MECHANICAL DESCRIPTION ..........................................................................................................239

38.1 LQFP (L) PACKAGE .............................................................................................................................239

38.2 CSBGA (G) PACKAGE ..........................................................................................................................240

5 of 240

Share Link: