DS2155 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2155

T1/E1/J1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

Figure 37-12. Transmit-Side Timing

tR

TCLK

TESO

TSER / TSIG /

TDATA

TCHCLK

TCHBLK

TSYNC1

TSYNC2

TLCLK5

TLINK

tF

t D1

t D2

tCP

tCL tCH

t SU

tHD

tD2

t SU

t D2

t HD

t D2

tHD

t SU

DS2155

Note 1: TSYNC is in the output mode (IOCR1.1 = 1).

Note 2: TSYNC is in the input mode (IOCR1.1 = 0).

Note 3: TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.

Note 4: TCHCLK and TCHBLK are synchronous with TCLK when the transmit-side elastic store is disabled.

Note 5: In E1 mode, TLINK is only sampled during Sa bit locations as defined in E1TCR2; no relationship between TLCLK/TLINK and TSYNC

is implied.

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