DS2155 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2155

T1/E1/J1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

Figure 37-9. Receive-Side Timing, Elastic Store Enabled

tR

RSYSCLK

tD3

RSER / RSIG

RCHCLK

RCHBLK

RMSYNC

RSYNC 1

2

RSYNC

tF

SEE NOTE 3

t D4

t D4

t D4

t D4

t HD

tSU

tSL tSH

tSP

Note 1: RSYNC is in the output mode.

Note 2: RSYNC is in the input mode.

Note 3: F-bit when MSTRREG.1 = 0, MSB of TS0 when MSTREG.1 = 1.

Figure 37-10. Receive Line Interface Timing

RCLKO

tDD

RPOSO, RNEGO

tR

RCLKI

RPOSI, RNEGI

tF

t SU

tLL tLH

t LP

tCL tCH

tCP

t HD

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DS2155

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