DS21552 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21552

3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers

Dallas Semiconductor -> Maxim Integrated 

2. LIST OF TABLES

DS21352/DS21552

Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER................................................................11

Table 4-2 PIN DESCRIPTION SORTED BY PIN SYMBOL ................................................................14

Table 5-1 REGISTER MAP SORTED BY ADDRESS...........................................................................29

Table 6-1 DEVICE ID BIT MAP .............................................................................................................33

Table 6-2 OUTPUT PIN TEST MODES .................................................................................................36

Table 7-1 RECEIVE T1 LEVEL INDICATION .....................................................................................47

Table 7-2 ALARM CRITERIA ................................................................................................................49

Table 8-1 LINE CODE VIOLATION COUNTING ARRANGEMENTS ..............................................53

Table 8-2 PATH CODE VIOLATION COUNTING ARRANGEMENTS.............................................54

Table 8-3 MULTIFRAMES OUT OF SYNC COUNTING ARRANGMENTS .....................................55

Table 14-1 ELASTIC STORE DELAY AFTER INITIALIZATION......................................................67

Table 14-2 MINIMUM DELAY MODE CONFIGURATION................................................................67

Table 15-1 TRANSMIT HDLC CONFIGURATION...............................................................................68

Table 15-2 HDLC/BOC CONTROLLER REGISTERS ..........................................................................70

Table 16-1 LINE BUILD OUT SELECT IN LICR .................................................................................86

Table16-2 TRANSMIT TRANSFORMER SELECTION .......................................................................87

Table 16-3 TRANSFORMER SPECIFICATIONS..................................................................................88

Table 16-4 PULSE TEMPLATE CORNER POINTS..............................................................................90

Table 16-5 RECEIVE MONITOR MODE GAIN....................................................................................95

Table 17-1 TRANSMIT CODE LENGTH...............................................................................................97

Table 17-2 RECEIVE CODE LENGTH ..................................................................................................97

Table 19-1 INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE .......................................104

Table 19-2 ID CODE STRUCTURE .....................................................................................................105

Table 19-3 DEVICE ID CODES ............................................................................................................105

Table 19-4 BOUNDARY SCAN CONTROL BITS ..............................................................................106

Table 20-1 MASTER DEVICE BUS SELECT.....................................................................................110

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