DS2153Q Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS2153Q Datasheet PDF : 52 Pages
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DS2153Q
of the unit. Quick access via the parallel control port allows a single micro to handle many E1 lines. The
device fully meets all of the latest E1 specifications, including ITU G.703, G.704, G.706, G.823, and
I.431 as well as ETSI 300 011, 300 233, TBR 12 and TBR 13.
TABLE OF CONTENTS
1. Introduction
2. Parallel Control Port
3. Control and Test Registers
4. Status and Information Registers
5. Error Count Registers
6. Sa Data Link Control and Operation
7. Signaling Operation
8. Transmit Idle Registers
9. Clock Blocking Registers
10. Elastic Store Operation
11. Additional (Sa) and International (Si) Bit Operation
12. Line Interface Control Function
13. Timing Diagrams, Synchronization Flowchart, and Transmit flow Diagram
14. DC and AC Characteristics
1.0 INTRODUCTION
The analog AMI waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of
the DS2153Q. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing
pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered E1 data stream and an asynchronous backplane clock which is
provided at the SYSCLK input.
The transmit side of the DS2153Q is totally independent from the receive side in both the clock
requirements and characteristics. The transmit formatter will provide the necessary data overhead for E1
transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation
mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP
and TRING pins via a coupling transformer.
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