DS2151 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2151

T1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

DS2151Q

DS2151Q latches the address from the AD0 to AD7 pins. Valid write data must be present and held

stable during the later portion of the DS or WR pulses. In a read cycle, the DS2151Q outputs a byte of

data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to

a high impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing.

The DS2151Q can also be easily connected to non-multiplexed buses. Please see the separate Application

Note for a detailed discussion of this topic.

3.0 CONTROL REGISTERS

The operation of the DS2151Q is configured via a set of eight registers. Typically, the control registers

are only accessed when the system is first powered up. Once the DS2151Q has been initialized, the

control registers will only need to be accessed when there is a change in the system configuration. There

are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and

TCR2), a Line Interface Control Register (LICR), and three Common Control Registers (CCR1, CCR2,

and CCR3). Seven of the eight registers are described below. The LICR is described in Section 12.

RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)

(MSB)

LCVCRF ARC

OOF1

OOF2 SYNCC SYNCT

(LSB)

SYNCE RESYNC

SYMBOL

LCVCRF

POSITION

RCR1.7

NAME AND DESCRIPTION

Line Code Violation Count Register Function Select.

0=do not count excessive 0s

1=count excessive 0s

ARC

RCR1.6

Auto Resync Criteria.

0=Resync on OOF or RCL event

1=Resync on OOF only

OOF1

RCR1.5

Out Of Frame Select 1.

0=2/4 frame bits in error

1=2/5 frame bits in error

OOF2

RCR1.4

Out Of Frame Select 2.

0=follow RCR1.5

1=2/6 frame bits in error

SYNCC

RCR1.3

Sync Criteria.

In D4 Framing Mode

0=search for Ft pattern, then search for Fs pattern

1=cross couple Ft and Fs pattern

In ESF Framing Mode

0=search for FPS pattern only

1=search for FPS and verify with CRC6

SYNCT

RCR1.2

Sync Time.

0=qualify 10 bits

1=qualify 24 bits

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