DS1870(2004) Просмотр технического описания (PDF) - Maxim Integrated
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DS1870 Datasheet PDF : 28 Pages
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LDMOS RF Power-Amplifier Bias
Controller
AC ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to 5.5V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (Figure 3)
PARAMETER
SCL Clock Frequency
Bus Free Time Between Stop and
Start Conditions
Hold Time (Repeated) Start
Condition
Low Period of SCL
High Period of SCL
Data Hold Time
Data Setup Time
Start Setup Time
SDA and SCL Rise Time
SYMBOL
fSCL (Note 7)
tBUF
tHD:STA
tLOW
tHIGH
tHD:DAT
tSU:DAT
tSU:STA
tR
(Note 8)
SDA and SCL Fall Time
Stop Setup Time
SDA and SCL Capacitive
Loading
EEPROM Write Time
tF
tSU:STO
CB
tW
(Note 8)
(Note 8)
(Note 9)
CONDITIONS
MIN TYP
0
1.3
0.6
1.3
0.6
0
100
0.6
20 +
0.1CB
20 +
0.1CB
0.6
10
MAX
400
UNITS
kHz
µs
µs
µs
µs
0.9
µs
ns
µs
300
ns
300
ns
µs
400
pF
20
ms
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +4.5V to 5.5V, TA = 0°C to +70°C.)
PARAMETER
SYMBOL
CONDITIONS
Writes
+70°C (Note 5)
MIN TYP
50,000
MAX UNITS
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
All voltages referenced to ground.
Supply current is measured with all logic inputs at their inactive state (SDA = SCL = VCC) and driven to well-defined logic
levels. All outputs are disconnected.
Absolute linearity is the difference of measured value from expected value at the DAC position. Expected value is a
straight line from measured minimum position to measured maximum position.
Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. Expected LSB change is
the slope of the straight line from measured minimum position to measured maximum position.
This parameter is guaranteed by design.
See Figure 1.
I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard-mode timing.
CB—total capacitance of one bus line in picofarads.
EEPROM write begins after a stop condition occurs.
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