DS1225Y-200 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS1225Y-200 Datasheet PDF : 8 Pages
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POWER-DOWN/POWER-UP CONDITION
DS1225Y
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL
CE at VIH before Power-Down
tPD
VCC Slew from VTP to 0V
tF
VCC Slew from 0V to VTP
tR
CE at VIH after Power-Up
tREC
MIN
0
100
0
PARAMETER
SYMBOL
Expected Data Retention Time
tDR
MIN
10
MAX
2
MAX
UNITS
ms
ms
ms
ms
UNITS
years
NOTES
11
(TA = 25°C)
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during a write cycle, the output buffers remain in a high impedance
state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write
Cycle 1, the output buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high-impedance state during this period.
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