DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

DM9000BI Просмотр технического описания (PDF) - Davicom Semiconductor, Inc.

Номер в каталоге
Компоненты Описание
производитель
DM9000BI Datasheet PDF : 56 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
DM9000BI
Industrial-grade Ethernet Controller with General Processor Interface
6.19 General purpose Register ( 1FH ) ( For 8 Bit mode only, for 16 bit mode, see reg . 34H)
Bit
Name
Default
Description
7 RESERVED 0,RO Reserved
6-4
GPO
P0,RW
General Purpose Output 6~4 (in 8-bit mode)
These bits are reflect to pin GP6~4 respectively.
General Purpose (in 8-bit mode)
3:1
GPIO
P0,RW
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is reflected to pin GP3~1 respectively.
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit to be read is reflected from correspondent pins of GP3~1 respectively.
PHY Power Down Control
0
PHYPD ET1,WO 1: power down PHY
0: power up PHY
6.20 TX SRAM Read Pointer Address Register (22H~23H)
Bit
Name
Default
Description
7:0 TRPAH PS0,RO TX SRAM Read Pointer Address High Byte (23H)
7:0 TRPAL PS0.RO TX SRAM Read Pointer Address Low Byte (22H)
6.21 RX SRAM Write Pointer Address Register (24H~25H)
Bit
Name
Default
Description
7:0 RWPAH PS,0CH,RO RX SRAM Write Pointer Address High Byte (25H)
7:0 RWPAL PS,00H.RO RX SRAM Write Pointer Address Low Byte (24H)
6.22 Vendor ID Register (28H~29H)
Bit
Name
Default
7:0
VIDH
PE,0AH,RO Vendor ID High Byte (29H)
7:0
VIDL
PE,46H.RO Vendor ID Low Byte (28H)
Description
6.23 Product ID Register (2AH~2BH)
Bit
Name
Default
7:0
PIDH
PE,90H,RO Product ID High Byte (2BH)
7:0
PIDL
PE,00H.RO Product ID Low Byte (2AH)
Description
6.24 Chip Revision Register (2CH)
Bit
Name
Default
7:0 CHIPR P,1AH,RO CHIP Revision
Description
6.25 Transmit Control Register 2 ( 2DH )
Bit
Name
Default
Description
Led Mode
7
LED
P0,RW When set, the LED pins act as led mode 1.
When cleared, the led mode is default mode 0 or depending EEPROM setting.
6
RLCP
P0,RW
Retry Late Collision Packet
Re-transmit the packet with late-collision
Preliminary
20
Version: DM9000BI-13-DS-P02
January 17, 2008

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]