DM9000BI Просмотр технического описания (PDF) - Davicom Semiconductor, Inc.

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производитель

DM9000BI

Industrial-grade Ethernet Controller with General Processor Interface

Davicom Semiconductor, Inc. 

RSCCR

MRCMDX

MRCMDX1

MRCMD

MRRL

MRRH

MWCMDX

MWCMD

MWRL

MWRH

TXPLL

TXPLH

ISR

IMR

DM9000BI

Industrial-grade Ethernet Controller with General Processor Interface

Resume System Clock Control Register

51H

XXH

Memory Data Pre-Fetch Read Command Without Address F0H

XXH

Increment Register

Memory Data Read Command With Address Increment F1H

XXH

Register

Memory Data Read Command With Address Increment F2H

XXH

Register

Memory Data Read_ address Register Low Byte

F4H

00H

Memory Data Read_ address Register High Byte

F5H

00H

Memory Data Write Command Without Address Increment F6H

XXH

Register

Memory Data Write Command With Address Increment F8H

XXH

Register

Memory Data Write_ address Register Low Byte

FAH

00H

Memory Data Write _ address Register High Byte

FBH

00H

TX Packet Length Low Byte Register

FCH

XXH

TX Packet Length High Byte Register

FDH

XXH

Interrupt Status Register

FEH

00H

Interrupt Mask Register

FFH

00H

Key to Default

In the register description that follows, the default column

takes the form:

<Reset Value>, <Access Type>

Where：

<Reset Value>:

1

Bit set to logic one

0

Bit set to logic zero

X

No default value

P = power on reset default value

S = software reset default value

E = default value from EEPROM

T = default value from strap pin

<Access Type>:

RO = Read only

RW = Read/Write

R/C = Read and Clear

RW/C1=Read/Write and Cleared by write 1

WO = Write only

Reserved bits are shaded and should be written with 0.

Reserved bits are undefined on read access.

6.1 Network Control Register (00H)

Bit

Name

Default

Description

7 RESERVED P0,RW Reserved

6

WAKEEN

When set, it enables the wakeup function. Clearing this bit will also clears all

P0,RW wakeup event status

This bit will not be affected after a software reset

5 RESERVED 0,RO Reserved

4

FCOL

PS0,RW Force Collision Mode, used for testing

3

FDX

PS0,RO Full-Duplex Mode of the internal PHY.

Loop-back Mode

Bit 2 1

2:1

LBK

PS00,

RW

0 0 Normal

0 1 MAC Internal Loop-back

1 0 Internal PHY 100M mode digital Loop-back

1 1 (Reserved)

0

RST

P0,RW Software reset and auto clear after 10us

Preliminary

14

Version: DM9000BI-13-DS-P02

January 17, 2008

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