DM74LS166N Просмотр технического описания (PDF) - Fairchild Semiconductor

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DM74LS166N

8-Bit Parallel-In/Serial-Out Shift Register

Fairchild Semiconductor 

Switching Characteristics

at VCC = 5V and TA = 25°C

Symbol

Parameter

From (Input)

To (Output)

fMAX

tPLH

tPHL

tPHL

Maximum Clock Frequency

Propagation Delay Time

LOW-to-HIGH Level Output

Propagation Delay Time

HIGH-to-LOW Level Output

Propagation Delay Time

HIGH-to-LOW Level Output

Clock to Output

Clock to Output

Clear to Output

Parameter Measurement Information

RL = 2 kΩ

CL = 15 pF

CL = 50 pF

Min

Max

Min

Max

25

20

8

35

38

8

35

41

6

30

36

Voltage Waveforms

Units

MHz

ns

ns

ns

Test Table for Synchronous Inputs

Data Input

Shift/Load

Output Tested

for Test

(See Note C)

H

Serial Input

0V

4.5V

QH at TN+1

QH at TN+8

Note A: The clock pulse has the following characteristics: tW(clock) ≥ 20 ns and PRR = 1 MHz. The clear pulse has the following characteristics:

tW(clear) ≥ 20 ns and tHOLD = 0 ns. When testing fMAX, vary the clock PRR.

Note B: A clear pulse is applied prior to each test.

Note C: Propagation delay times (tPLHand tPHL) are measured at tn+1. Proper shifting of data is verified at tn+8 with a functional test.

Note D: tn = bit time before clocking transition

tn+1 = bit time after one clocking transition

tn+8 = bit time after eight clocking transitions

Note E: VREF = 1.3V.

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