MAX5120 Просмотр технического описания (PDF) - Maxim Integrated
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MAX5120 Datasheet PDF : 20 Pages
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+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX5121 (+3V) (continued)
(VDD = +3V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input Leakage Current
IIN
VIN = 0 or VDD
-1 0.001
1
µA
Input Capacitance
CIN
8
pF
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
VOH
VOL
ISOURCE = 2mA
ISINK = 2mA
VDD - 0.5
V
0.13
0.4
V
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
0.6
V/µs
Output Settling Time
To ±0.5LSB, VSTEP = 2V
20
µs
Output Voltage Swing (Note 4)
0 to VDD
V
OS Input Resistance
ROS
Time Required to Exit Shutdown
83
121
kΩ
2
ms
Digital Feedthrough
CS = VDD, fSCLK = 100kHz,
VSCLK = 3Vp-p
5
nV-s
POWER REQUIREMENTS
Power-Supply Voltage (Note 5)
VDD
2.7
3.6
V
Power-Supply Current (Note 5)
IDD
500
600
µA
Power-Supply Current in Shutdown
ISHDN
3
20
µA
TIMING CHARACTERISTICS—MAX5120 (+5V)
(VDD = +5V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCLK Clock Period
tCP
100
ns
SCLK Pulse Width High
tCH
40
ns
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
tCL
tCSS
tCSH
40
ns
40
ns
0
ns
SDI Setup Time
tDS
40
ns
SDI Hold Time
tDH
0
ns
SCLK Rise to DOUT Valid
Propagation Delay Time
tDO1
CLOAD = 200pF
80
ns
SCLK Fall to DOUT Valid
Propagation Delay Time
SCLK Rise to CS Fall Delay Time
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
tDO2
tCS0
tCS1
tCSW
CLOAD = 200pF
80
ns
10
ns
40
ns
100
ns
4 _______________________________________________________________________________________
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