GS818DV18D-300 Просмотр технического описания (PDF) - Giga Semiconductor

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GS818DV18D-300

18Mb Σ2x2B4V SigmaQuad SRAM

Giga Semiconductor 

Preliminary

GS818DV18D-333/300/250/200

165-Bump BGA

Commercial Temp

Industrial Temp

18Mb Σ2x2B4V

SigmaQuad SRAM

200 MHz–333 MHz

2.5 V VDD

1.8 V and 1.5 V I/O

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual DoubleData Rate interface

• Echo Clock outputs track data output drivers

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 2.5 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices

tKHKH

tKHQV

- 333

3.0 ns

1.6 ns

-300

3.3 ns

1.8 ns

-250

4 ns

2.1 ns

-200

5 ns

2.3 ns

SigmaRAM™ Family Overview

GS818DV18 are built in compliance with the SigmaQuad SRAM

pinout standard for Separate I/O synchronous SRAMs. They

are18,874,368-bit (18Mb) SRAMs. These are the first in a family of

wide, very low voltage HSTL I/O SRAMs designed to operate at the

speeds needed to implement economical high performance

networking systems.

SigmaQuad SRAMs are offered in a number of configurations. Some

emulate and enhance other synchronous separate I/O SRAMs. A

higher performance SDR (Single Data Rate) Burst of 2 versionis also

offered. The logical differences between the protocols employed by

these RAMs hinge mainly on various combinations of address

bursting, output data registering, and write cueing. Along with the

Common I/O family of SigmaRAMs, the SigmaQuad family of SRAMs

allows a user to implement the interface protocol best suited to the

task at hand.

Bottom View

165-Bump, 13 mm x 15 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

JEDEC Std. MO-216, Variation CAB-1

Clocking and Addressing Schemes

A Σ2x2B4SigmaQuad SRAM is a synchronous device. It employs two

input register clock inputs, K and K. K and K are independent single-

ended clock inputs, not differential inputs to a single differential clock

input buffer. The device also allows the user to manipulate the output

register clock inputs quasi independently with the C and C clock

inputs. C and C are also independent single-ended clock inputs, not

differential inputs. If the C clocks are tied high, the K clocks are routed

internally to fire the output registers instead. Each Σ2x2B4 igmaQuad

SRAM also supplies Echo Clock outputs, CQ and CQ, that are

synchronized with read data output. When used in a source

synchronous clocking scheme, these Echo Clock outputs can be used

to fire input registers at the data’s destination.

Because Separate I/O Σ2x2B4 RAMs always transfer data in four

packets, A0 and A1 are internally set to 0 for the first read or write

transfer, and automatically incremented by 1 for the next transfers.

Because the LSBs are tied off internally, the address field of a

Σ2x2B4 RAM is always two address pins less than the advertised

index depth (e.g., the 1M x 18 has a 256K addressable index).

Rev: 1.01 11/2002

1/26

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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