DAC1627D1G25 Просмотр технического описания (PDF) - NXP Semiconductors.

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DAC1627D1G25

Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating

NXP Semiconductors. 

NXP Semiconductors

DAC1627D1G25

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

DAC1627D1G25

Objective data sheet

Table 2. Pin description …continued

Symbol

Pin

Type[1] Description

LD[14]P

10

I

LVDS positive input bit 14[2]

LD[14]N

11

I

LVDS negative input bit 14[2]

VDDD(1V8)

LD[13]P

12

P

13

I

1.8 V digital power supply

LVDS positive input bit 13[2]

LD[13]N

14

I

LVDS negative input bit 13[2]

LD[12]P

15

I

LVDS positive input bit 12[2]

LD[12]N

16

I

LVDS negative input bit 12[2]

LD[11]P

17

I

LVDS positive input bit 11[2]

LD[11]N

18

I

LVDS negative input bit 11[2]

VDDD(1V8)

LD[10]P

19

P

20

I

1.8 V digital power supply

LVDS positive input bit 10[2]

LD[10]N

21

I

LVDS negative input bit 10[2]

LD[9]P

22

I

LVDS positive input bit 9[2]

LD[9]N

23

I

LVDS negative input bit 9[2]

LD[8]P

24

I

LVDS positive input bit 8[2]

LD[8]N

25

I

LVDS negative input bit 8[2]

VDDD(1V8)

LCKP

26

P

27

I

1.8 V digital power supply

LVDS positive data clock input

LCKN

28

I

LVDS negative data clock input

GND_DP

29

G

connect to ground

LD[7]P

30

I

LVDS positive input bit 7[2]

LD[7]N

31

I

LVDS negative input bit 7[2]

LD[6]P

32

I

LVDS positive input bit 6[2]

LD[6]N

33

I

LVDS negative input bit 6[2]

LD[5]P

34

I

LVDS positive input bit 5[2]

LD[5]N

35

I

LVDS negative input bit 5[2]

VDDD(1V8)

LD[4]P

36

P

37

I

1.8 V digital power supply

LVDS positive input bit 4[2]

LD[4]N

38

I

LVDS negative input bit 4[2]

LD[3]P

39

I

LVDS positive input bit 3[2]

LD[3]N

40

I

LVDS negative input bit 3[2]

LD[2]P

41

I

LVDS positive input bit 2[2]

LD[2]N

42

I

LVDS negative input bit 2[2]

VDDD(1V8)

LD[1]P

43

P

44

I

1.8 V digital power supply

LVDS positive input bit 1[2]

LD[1]N

45

I

LVDS negative input bit 1[2]

LD[0]P

46

I

LVDS positive input bit 0[2]

LD[0]N

47

I

LVDS negative input bit 0[2]

IO1

48

IO

IO port bit 1

IO0

49

IO

IO port bit 0

SDO

50

O

SPI data output

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 29 April 2011

© NXP B.V. 2011. All rights reserved.

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