D8259 Просмотр технического описания (PDF) - Digital Core Design
Номер в каталоге
Компоненты Описание
производитель
D8259 Datasheet PDF : 4 Pages
| |||
BLOCK DIAGRAM
Read Write Logic - The Read/Write Logic
accepts inputs from the system bus and gen-
erates control signals for the other functional
blocks of the D8259. A “low'' on the RD input
tells the D8259 that the CPU is reading con-
tents of IRR and ISR registers. A “low'' on the
WR input tells the D8254 that the CPU is writ-
ing a Command Words to D8259. Both RD
and WR are qualified by CS; RD and WR are
ignored unless the D8259 has been selected
by holding CS low.
Data Bus Buffer 8-bit buffer is used to inter-
face the D8259 to the system bus.
rst
a0
wr
rd
cs
datai(7:0)
datao(7:0)
dbe
casi(2:0)
caso(2:0)
case
sp
en
Read/Write
Logic
Data Bus
Buffer
Cascade
Controller
inta
Control logic
int
ir7
ir6
Interrupt
ir5
Request
ir4
Register
ir3
ir2
ir1
ir0
Priority
resolver
Interrupt
Mask
Register
In Service
Register
Cascade Controller - The Cascade Con-
troller stores and compares Identifiers of
all 8259 devices in the system. Block
manages direction of CAS input/output
buses, depending of device status: Mas-
ter or Slave. When operating as a master
the D8259 drives onto the CAS bus ad-
dress of interrupting 8259 device, then
the addressed 8259 slave during the next
one or two consecutive INTA pulses send
to the Data Bus preprogrammed address
of subroutine.
Interrupt Mask Register – IMR register
stores the information which interrupt re-
quest to be masked.
Control Logic – CL block checks for
INTA pulses, which cause the D8259 to
release vectoring information onto the
Data Bus. Format of drive data depends
on mode of operation. CL also manages
state of INT output.
Interrupt Request Register – IIR regis-
ter stores information about states of all
IR lines. It saves information about all
interrupt requests to be serviced.
Priority Resolver – PR block resolve
which interrupt request has the highest
priority, and will be served as first.
In Service Register– ISR register stores
information about interrupts that are being
serviced.
PERFORMANCE
The following table gives a survey about
the Core area and performance in the AL-
TERA® devices after Place & Route:
Device
Speed
grade
Logic Cells
Fmax
CYCLONE
-6
394
154 MHz
CYCLONE 2 -6
387
163 MHz
STRATIX
-5
394
164 MHz
STRATIX 2
-3
294
239 MHz
STRATIXGX -5
394
166 MHz
MERCURY
-5
435
181 MHz
EXCALIBUR -1
407
99 MHz
APEX II
-7
407
136 MHz
APEX20KC -7
407
110 MHz
APEX20KE
-1
407
93 MHz
APEX20K
-1V
407
72 MHz
ACEX1K
-1
413
78 MHz
FLEX10KE
-1
413
76 MHz
Core performance in ALTERA® devices
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
Share Link: 