CY8C5246PVI-091 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY8C5246PVI-091

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC®5: CY8C52 Family Data Sheet

Figure 2-2. 68-Pin QFN Part Pinout[3]

(TRACEDATA[2], GPIO) P2[6] 1

(TRACEDATA[3], GPIO) P2[7] 2

(I2C0: SCL, SIO) P12[4] 3

(I2C0: SDA, SIO) P12[5] 4

Vssb 5

Ind 6

Vboost 7

Vbat 8

Vssd 9

XRES 10

(TMS, SWDIO, GPIO) P1[0] 11

(TCK, SWDCK, GPIO) P1[1] 12

(configurable XRES, GPIO) P1[2] 13

(TDO, SWV, GPIO) P1[3] 14

(TDI, GPIO) P1[4] 15

(nTRST, GPIO) P1[5] 16

Vddio1 17

Lines show Vddio

to IO supply

association

QFN

(Top View)

51 P0[3] (GPIO, Extref0)

50 P0[2] (GPIO)

49 P0[1] (GPIO)

48 P0[0] (GPIO)

47 P12[3] (SIO)

46 P12[2] (SIO)

45 Vssd

44 Vdda

43 Vssa

42 Vcca

41 P15[3] (GPIO, kHz XTAL: Xi)

40 P15[2] (GPIO, kHz XTAL: Xo)

39 P12[1] (SIO, I2C1: SDA)

38 P12[0] (SIO, 12C1: SCL)

37 P3[7] (GPIO)

36 P3[6] (GPIO)

35 Vddio3

Notes

2. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.

3. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

Document Number: 001-55034 Rev. *A

Page 6 of 85

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