CY8C3666LTI-046(2010) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY8C3666LTI-046 Datasheet PDF : 112 Pages
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PRELIMINARY
PSoC® 3: CY8C36 Family Datasheet
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
Vssa
Vddd
Vssd
Vdda
Vssd
Plane
Vssa
Plane
3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3. Low resistance output pin for
high current DACs (IDAC).
OpAmp0out, OpAmp1out[15], OpAmp2out, OpAmp3out[15].
High current output of uncommitted opamp.[14]
Extref0, Extref1. External reference input to the analog system.
OpAmp0–, OpAmp1–[15], OpAmp2–, OpAmp3–[15]. Inverting
input to uncommitted opamp.
OpAmp0+, OpAmp1+[15], OpAmp2+, OpAmp3+[15].
Noninverting input to uncommitted opamp.
GPIO. General purpose I/O pin provides interfaces to the CPU,
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense.[14]
I2C0: SCL, I2C1: SCL. I2C SCL line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SCL if
wake from sleep is not required.
I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SDA if
wake from sleep is not required.
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33 MHz crystal oscillator pin.
nTRST. Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
SIO. Special I/O provides interfaces to the CPU, digital
peripherals and interrupts with a programmable high threshold
voltage, analog comparator, high sink current, and high
impedance state when the device is unpowered.
SWDCK. Serial wire debug clock programming and debug port
connection.
SWDIO. Serial wire debug input and output programming and
debug port connection.
SWV. Single wire viewer debug output.
TCK. JTAG test clock programming and debug port connection.
TDI. JTAG test data in programming and debug port connection.
TDO. JTAG test data out programming and debug port
connection.
TMS. JTAG test mode select programming and debug port
connection.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin. Pins are Do Not Use (DNU) on
devices without USB.
USBIO, D–. Provides D– connection directly to a USB 2.0 bus.
May be used as a digital I/O pin. Pins are Do Not Use (DNU) on
devices without USB.
Vboost. Power sense connection to boost pump.
Vbat. Battery supply to boost pump.
Vcca. Output of analog core regulator and input to analog core.
Requires a 1-µF capacitor to Vssa. Regulator output not for
external use.
Notes
14. GPIOs with opamp outputs are not recommended for use with CapSense.
15. This feature on select devices only. See Ordering Information on page 100 for details.
Document Number: 001-53413 Rev. *I
Page 10 of 112
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