CY8C3246PVI-122(2012) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY8C3246PVI-122 Datasheet PDF : 122 Pages
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PSoC® 3: CY8C32 Family
Data Sheet
This enables the device to be powered directly from a single
battery or solar cell. In addition, you can use the boost converter
to generate other voltages required by the device, such as a
3.3-V supply for LCD glass drive. The boost’s output is available
on the VBOOST pin, allowing other devices in the application to
be powered from the PSoC.
PSoC supports a wide range of low-power modes. These include
a 200-nA hibernate mode with RAM retention and a 1-µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz, or 0.8 mA running at 3 MHz.
The details of the PSoC power modes are covered in the “Power
System” section on page 29 of this datasheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. The 1-wire SWV may also be
used for “printf” style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins.
Using these standard interfaces enables you to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. PSoC supports on-chip break
points and 4-KB instruction and data race memory for debug.
Details of the programming, test, and debugging interfaces are
discussed in the “Programming, Debug Interfaces, Resources”
section on page 59 of this datasheet.
2. Pinouts
Each VDDIO pin powers a specific set of I/O pins. (The USBIOs
are powered from VDDD.) Using the VDDIO pins, a single PSoC
can support multiple voltage levels, reducing the need for
off-chip level shifters. The black lines drawn on the pinout
diagrams in Figure 2-3 through Figure 2-6 show the pins that are
powered by each VDDIO.
Each VDDIO may source up to 100 mA total to its associated I/O
pins, as shown in Figure 2-1.
Figure 2-1. VDDIO Current Limit
IDDIO X = 100 mA
VDDIO X
I/O Pins
PSoC
Conversely, for the 100-pin and 68-pin devices, the set of I/O
pins associated with any VDDIO may sink up to 100 mA total, as
shown in Figure 2-2.
Figure 2-2. I/O Pins Current Limit
Ipins = 100 mA
VDDIO X
I/O Pins
PSoC
VSSD
For the 48-pin devices, the set of I/O pins associated with
VDDIO0 plus VDDIO2 may sink up to 100 mA total. The set of
I/O pins associated with VDDIO1 plus VDDIO3 may sink up to a
total of 100 mA.
Document Number: 001-56955 Rev. *N
Page 5 of 122
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