CY8C20437S-24LKXCT Просмотр технического описания (PDF) - Cypress Semiconductor
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CY8C20437S-24LKXCT
Cypress Semiconductor
CY8C20437S-24LKXCT Datasheet PDF : 43 Pages
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CY8C20xx7/S
24-pin QFN (16 Sensing Inputs)[11]
Table 3. Pin Definitions – CY8C20337, CY8C20347/S [12]
Pin
No.
Type
Digital Analog
Name
Description
1
I/O
I P2[5] Crystal output (XOut)
2
I/O
I P2[3] Crystal input (XIn)
3
I/O
4 IOHR
5 IOHR
I P2[1]
I P1[7] I2C SCL, SPI SS
I P1[5] I2C SDA, SPI MISO
6 IOHR
7 IOHR
I P1[3] SPI CLK
I
P1[1] ISSP CLK[13], I2C SCL, SPI
MOSI
8
NC No connection
9
Power
10 IOHR
I
VSS
P1[0]
Ground connection
CISLSKP[1D4]ATA[13], I2C SDA, SPI
11 IOHR
I P1[2] Driven Shield Output
(optional)
12 IOHR
I P1[4] Optional external clock input
(EXTCLK)
13 IOHR
I P1[6]
14
Input
XRES Active high external reset
with internal pull-down
15 I/O
I P2[2] Driven Shield Output
(optional)
16 I/O
I P2[4] Driven Shield Output
(optional)
17 IOH
I P0[0] Driven Shield Output
(optional)
18 IOH
I P0[2] Driven Shield Output
(optional)
19 IOH
I P0[4]
20
Power
21 IOH
I
VDD Supply voltage
P0[7]
22 IOH
I P0[3] Integrating input
23
Power
24 IOH
I
VSS Ground connection
P0[1] Integrating input
CP
Power
VSS
Center pad must be
connected to ground
Figure 4. CY8C20337, CY8C20347/S Device
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, P2[1]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
1
18
2
17
3 QFN 16
4 (Top View) 15
5
14
6
13
P0[2], AI
P0[0], AI
P2[4], AI
P2[2], AI
XRES
P1[6], AI
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
11.
The center pad (CP) on the QFN
it must be electrically floated and
package must be
not connected to
connected to ground
any other signal.
(VSS)
for
best
mechanical,
thermal,
and
electrical
performance.
If
not
connected
to
ground,
12. 19 GPIOs = 16 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
13. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive
resistive
low
low
for
for
512 sleep clock cycles and both the pins transition to
8 sleep clock cycles and transition to high impedance
high impedance state. On reset, after XRES de-asserts,
state. Hence, during power-up or reset event, P1[1] and
the SDA and the SCL
P1[0] may disturb the
lIi2nCesbdusri.vUe se
alternate pins if you encounter issues.
14. Alternate SPI clock.
Document Number: 001-69257 Rev. *I
Page 9 of 43
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