CY8C20437S-24LKXCT Просмотр технического описания (PDF) - Cypress Semiconductor
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CY8C20437S-24LKXCT
Cypress Semiconductor
CY8C20437S-24LKXCT Datasheet PDF : 43 Pages
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CY8C20xx7/S
32-pin QFN (25 Sensing Inputs)[18]
Table 5. Pin Definitions – CY8C20437, CY8C20447/S, CY8C20467/S [19]
Pin
No.
Type
Digital Analog
Name
Description
Figure 6. CY8C20437, CY8C20447/S, CY8C20467/S Device
1
IOH
I
P0[1] Integrating input
2
I/O
I
P2[5] Crystal output (XOut)
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
IOHR
9
IOHR
I
P2[3] Crystal input (XIn)
I
P2[1]
I
P4[3]
I
P3[3]
I
P3[1]
I
P1[7] I2C SCL, SPI SS
I
P1[5] I2C SDA, SPI MISO
AI , XOut,P0[1] 1
AI , XIn ,P2[5] 2
AI ,P2[3] 3
AI ,P2[1] 4
AI ,P4[3] 5
AI ,P3[3] 6
AI ,P3[1] 7
AI ,I2 C SCL, SPI SS,P1[7] 8
24 P2[4] ,AI
23 P2[2] ,AI
22 P2[0] ,AI
QFN
21 P4[2] ,AI
(Top View) 20 P4[0] ,AI
19 P3[2] ,AI
18 P3[0] ,AI
17 XRES
10 IOHR
11 IOHR
I
P1[3] SPI CLK.
I
P1[1] ISSP CLK[20], I2C SCL, SPI
MOSI.
12
Power
13 IOHR
I
VSS
P1[0]
Ground connection
SISPSIPCDLKA[T2A1][20], I2C SDA,
14 IOHR
I
P1[2] Driven Shield Output (optional)
15 IOHR
I
P1[4] Optional external clock input
(EXTCLK)
16 IOHR
I
P1[6]
17
Input
XRES Active high external reset with
internal pull-down
18
I/O
I
P3[0]
19
I/O
I
P3[2]
20
I/O
I
P4[0]
21
I/O
I
P4[2]
22
I/O
I
P2[0]
23
I/O
I
P2[2] Driven Shield Output (optional)
24
I/O
I
P2[4] Driven Shield Output (optional)
25 IOH
I
P0[0] Driven Shield Output (optional)
26 IOH
I
P0[2] Driven Shield Output (optional)
27 IOH
I
P0[4]
28 IOH
I
P0[6]
29
Power
30 IOH
I
VDD
P0[7]
31 IOH
I
P0[3] Integrating input
32
Power
VSS Ground connection
CP
Power
VSS
Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
18.
The center pad (CP) on the QFN
it must be electrically floated and
package must be
not connected to
connected to ground
any other signal.
(VSS)
for
best
mechanical,
thermal,
and
electrical
performance.
If
not
connected
to
ground,
19. 28 GPIOs = 25 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
20. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
21. Alternate SPI clock.
Document Number: 001-69257 Rev. *I
Page 11 of 43
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