CY3681 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY3681 Datasheet PDF : 48 Pages
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CY7C68013
Port
56
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
IFCLK
CLKOUT
DPLUS
DMINUS
BKPT
100
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
D7
D6
D5
D4
D3
D2
D1
D0
128
EA
GPIF Master
PD7 FD[15]
PD6 FD[14]
PD5 FD[13]
PD4 FD[12]
PD3 FD[11]
PD2 FD[10]
PD1 FD[9]
PD0 FD[8]
PB7 FD[7]
PB6 FD[6]
PB5 FD[5]
PB4 FD[4]
PB3 FD[3]
PB2 FD[2]
PB1 FD[1]
PB0 FD[0]
RDY0
RDY1
CTL0
CTL1
CTL2
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
TIMER2
TIMER1
TIMER0
RD#
WR#
CS#
OE#
PSEN#
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Figure 4-1. Signals
Slave FIFO
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
SLRD
SLWR
FLAGA
FLAGB
FLAGC
INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
Document #: 38-08012 Rev. *E
Page 11 of 48
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