CY3681 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY3681 Datasheet PDF : 48 Pages
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CY7C68013
3.16 Autopointer Access
FX2 provides two identical autopointers. They are similar to
the internal 8051 data pointers, but with an additional feature:
they can optionally increment a pointer address after every
memory access. This capability is available to and from both
internal and external RAM. The autopointers are available in
external FX2 registers, under control of a mode bit (AUTOP-
TRSETUP.0). Using the external FX2 autopointer access (at
0xE67B – 0xE67C) allows the autopointer to access all RAM,
internal and external to the part. Also, the autopointers can
point to any FX2 register or endpoint buffer space. When
autopointer access to external memory is enabled, location
0xE67B and 0xE67C in XDATA and PDATA space cannot be
used.
3.17 I2C-compatible Controller
FX2 has one I2C-compatible port that is driven by two internal
controllers, one that automatically operates at boot time to
load VID/PID/DID and configuration information, and another
that the 8051, once running, uses to control external I2C-
compatible devices. The I2C-compatible port operates in
master mode only.
3.17.1 I2C-compatible Port Pins
The I2C-compatible pins SCL and SDA must have external
2.2-kΩ pull-up resistors. External EEPROM device address
pins must be configured properly. See Table 3-7 for config-
uring the device address pins.
Table 3-7. Strap Boot EEPROM Address Lines to These
Values
Bytes Example EEPROM A2
A1
A0
16
24LC00[4]
N/A
N/A
N/A
128 24LC01
0
0
0
256 24LC02
0
0
0
4K
24LC32
0
0
1
8K
24LC64
0
0
1
Note:
4. This EEPROM does not have address pins.
3.17.2 I2C-compatible Interface Boot Load Access
At power-on reset the I2C-compatible interface boot loader will
load the VID/PID/DID/a configuration byte and up to eight
kbytes of program/data. The available RAM spaces are eight
kbytes from 0x0000–0x1FFF and 512 bytes from
0xE000–0xE1FF. The 8051 will be in reset. I2C-compatible
interface boot loads only occur after power-on reset.
3.17.3 I2C-compatible Interface General Purpose Access
The 8051 can control peripherals connected to the I2C-
compatible bus using the I2CTL and I2DAT registers. FX2
provides I2C compatible master control only, it is never an I2C-
compatible slave.
4.0 Pin Assignments
Figure 4-1 identifies all signals for the four package types. The
following pages illustrate the individual pin diagrams, plus a
combination diagram showing which of the full set of signals
are available in the 128-, 100-, and 56-pin packages.
The 56-pin package is the lowest-cost version. The signals on
the left edge of the 56-pin package in Figure 4-1 are common
to all versions in the FX2 family. Three modes are available in
all package versions: Port, GPIF master, and Slave FIFO.
These modes define the signals on the right edge of the
diagram. The 8051 selects the interface mode using the
IFCONFIG[1:0] register bits. Port mode is the power-on default
configuration.
The 100-pin package adds functionality to the 56-pin package
by adding these pins:
• PORTC or alternate GPIFADR[7...0] address signals
• PORTE or alternate GPIFADR8 address signals and 7 more
8051 signals
• Three GPIF Control signals
• Four GPIF Ready signals
• Nine 8051 signals (two USARTs, three timer inputs,
INT4,and INT5#)
• BKPT, RD#, WR#
The 128-pin package is the full version, adding the 8051
address and data buses plus control signals. Note that two of
the required signals, RD# and WR#, are present in the 100-pin
version. In the 100-pin and 128-pin versions, an 8051 control
bit can be set to pulse the RD# and WR# pins when the 8051
reads from/writes to PORTC.
Document #: 38-08012 Rev. *E
Page 10 of 48
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