CY62256VL-70ZC(1996) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY62256VL-70ZC Datasheet PDF : 10 Pages
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PRELIMINARY
CY62256V
Switching Characteristics Over the Operating Range[5] (continued)
Parameter
WRITE CYCLE[8,9]
Description
tWC
Write Cycle Time
tSCE
CE LOW to Write End
tAW
Address Set-Up to Write End
tHA
Address Hold from Write End
tSA
Address Set-Up to Write Start
tPWE
WE Pulse Width
tSD
Data Set-Up to Write End
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High Z[6, 7]
WE HIGH to Low Z[6]
Shaded area contains advanced information.
Switching Waveforms
Read Cycle No. 1[10, 11]
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tRC
[10, 11]
tAA
Read Cycle No. 2 [11, 12]
t RC
CE
CY62256V-55
Min.
Max.
CY62256V-70
Min.
Max.
55
70
45
60
45
60
0
0
0
0
40
50
25
30
0
0
20
25
3
3
DATA VALID
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C62256V–8
tACE
OE
DATA OUT
VCC
SUPPLY
CURRENT
tDOE
t LZOE
HIGH IMPEDANCE
tLZCE
t PU
50%
DATA VALID
t HZOE
tHZCE
HIGH
IMPEDANCE
t PD
50%
ICC
ISB
C62256V–9
Notes:
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
5
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