CY7C457 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C457
Cypress Semiconductor
CY7C457 Datasheet PDF : 23 Pages
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Switching Waveforms (continued)
Read to Empty Timing Diagram[22, 25, 26]
COUNT
3
2
1
CKR
ENR
R1
ENABLED
READ
ENARB2LED
READ
CKW
ENW
LOW
E/F
CY7C455
CY7C456
CY7C457
0
1
R3
ENABLED
READ
1 (NO CHANGE)
0
LATENT CYCLE
R4
FLAG
UPDATE
READ
R5
ENABLED
READ
tSKEW1
tSKEW2
W1
ENABLED
WRITE
tFD
tFD
tFD
Read to Empty Timing Diagram with Free-RunningClocks[22, 23, 24, 25]
COUNT
CKR
ENR
1
0
R1
ENABLED
READ
R2
IGNORED
READ
1
R3
IGNORED
READ
tSKEW2
LATENT CYCLE
R4
FLAG
UPDATE
READ
0
R5
ENABLED
READ
CKW
tSKEW1
tSKEW2
W1
W2
W3
W4
W5
ENABLED
WRITE
ENW
c455-12
R6
IGNORED
READ
W6
HF
HIGH
tFD
E/F
PAFE
LOW
tFD
tFD
c455-11
Notes:
22. “Count” is the number of words in the FIFO.
23. The FIFO is assumed to be programmed with P>0 (i.e., PAFE does not transition at Empty or Full).
24. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs
less than tSKEW2 before R3. Therefore, the FIFO still appears empty when R3 occurs. Because W3 occurs greater than tSKEW2 before R4, R4 includes
W3 in the flag update.
25. CKR is clock and CKW is opposite clock.
26. R3 updates the flag to the Empty state by asserting E/F. Because W1 occurs greater than tSKEW1 after R3, R3 does not recognize W1 when updating
flag status. But because W1 occurs tSKEW2 before R4, R4 includes W1 in the flag update and, therefore, updates FIFO to Almost Empty state. It is
important to note that R4 is a latent cycle; i.e., it only updates the flag status regardless of the state of ENR. It does not change the count or the
FIFO’s data outputs.
Document #: 38-06003 Rev. *A
Page 9 of 23
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