CY7C455 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C455

512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags

Cypress Semiconductor 

CY7C455

CY7C456

CY7C457

Switching Waveforms (continued)

Master Reset (Programming Mode) Timing Diagram[20, 21]

tSMRP

MR

tHMRP

CKW

ENW LOW

tSCMR

LAST

VALID

WRITE

tCKH

tSD

PGM

WRITE

tFTP

tHD

D0 − 17

CKR

ENR

LAST

WORD

tSCMR

LOW

LAST

VALID

READ

PGM

WORD

tSMRP

PGM

READ

tCKH

tMRR

FIRST

WRITE

SECOND

WRITE

WORD 1

tHMRP

WORD 2

Q0 − 17

tOHMR

VALID DATA

tAP

tOHP

PGM WORD

tAMR

Master Reset (Programming Mode with Free-Running Clocks) Timing Diagram[20, 21]

ALL DATA

OUTPUTS LOW

c455-9

MR

CKW

tSCMR

LAST

VALID

WRITE

ENW

tSMRP

tCKH

tSEN

tCKW

PGM

WRITE

tHEN

tHMRP

tCKL

tMRR

FIRST

WRITE

SECOND

WRITE

D0 − 17

LAST

WORD

CKR

tSCMR

LAST

VALID

READ

ENR

Q0 − 17

tOHMR

VALID DATA

PGM

WORD

tFTP

tSMRP

tSEN

tCKH

tCKR

PGM

READ

tHEN

tHMRP

tCKL

WORD 1

tMRR

tAMR

tAP

tOHP

PGM WORD

WORD 2

ALL DATA

OUTPUTS LOW

c455-10

Document #: 38-06003 Rev. *A

Page 8 of 23

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