CY7C457 Просмотр технического описания (PDF) - Cypress Semiconductor
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производитель
CY7C457
Cypress Semiconductor
CY7C457 Datasheet PDF : 23 Pages
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CY7C455
CY7C456
CY7C457
Switching Characteristics Over the Operating Range[14]
7C455/6/7– 7C455/6/7– 7C455/6/7– 7C455/6/7–
12
14
20
30
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCKW
Write Clock Cycle
12
14
20
30
ns
tCKR
Read Clock Cycle
12
14
20
30
ns
tCKH
Clock HIGH
5
6.5
9
12
ns
tCKL
Clock LOW
5
6.5
9
12
ns
tA
Data Access Time
9
10
15
20 ns
tOH
Previous Output Data Hold After Read HIGH
0
0
0
0
ns
tFH
Previous Flag Hold After Read/Write HIGH
0
0
0
0
ns
tSD
Data Set-Up
4
5
6
7
ns
tHD
Data Hold
0
0
0
0
ns
tSEN
Enable Set-Up
4
5
6
7
ns
tHEN
Enable Hold
0
0
0
0
ns
tOE
tOLZ[8, 15]
tOHZ[8, 15]
OE LOW to Output Data Valid
OE LOW to Output Data in Low Z
OE HIGH to Output Data in High Z
9
10
15
20 ns
0
0
0
0
ns
9
10
15
20 ns
tPG
Read HIGH to Parity Generation
9
10
15
20 ns
tPE
Read HIGH to Parity Error Flag
9
10
15
20 ns
tFD
tSKEW1[16]
tSKEW2[17]
Flag Delay
Opposite Clock After Clock
Opposite Clock Before Clock
9
10
15
20 ns
0
0
0
0
ns
12
14
20
30
ns
tPMR
Master Reset Pulse Width (MR LOW)
14
14
20
30
ns
tSCMR
Last Valid Clock LOW Set-Up to MR LOW
0
0
0
0
ns
tOHMR
Data Hold From MR LOW
0
0
0
0
ns
tMRR
Master Reset Recovery
12
14
20
30
ns
(MR HIGH Set-Up to First Enabled Write/Read)
tMRF
MR HIGH to Flags Valid
12
14
20
30 ns
tAMR
MR HIGH to Data Outputs LOW
12
14
20
30 ns
tSMRP
Program Mode—MR LOW Set-Up
12
14
20
30
ns
tHMRP
Program Mode—MR LOW Hold
9
10
15
20
ns
tFTP
Program Mode—Write HIGH to Read HIGH
12
14
20
30
ns
tAP
Program Mode—Data Access Time
12
14
20
30 ns
tOHP
Program Mode—Data Hold Time from MR HIGH 0
0
0
0
ns
tPRT
Retransmit Pulse Width
12
14
20
30
ns
tRTR
Retransmit Recovery Time
12
14
20
30
ns
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and
Waveforms and capacitance as in notes 9 and 10, unless otherwise specified.
15. At any given temperature and voltage condition, tOLZ is greater than tOHZ for any given device.
16. tSKEW1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle
(for purposes of flag update). If the opposite clock occurs less than tSKEW1 after the clock, the decision of whether or not to include the
opposite clock in the current clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is
the opposite clock for Empty and Almost Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal
to which a flag is synchronized; i.e., CKW is the clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags.
17. tSKEW2 is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEW2 before the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. See Note 16 for definition of clock and opposite clock.
Document #: 38-06003 Rev. *A
Page 6 of 23
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