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CY7C457

512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags

Cypress Semiconductor 

CY7C455

CY7C456

CY7C457

Pin Definitions

Signal Name I/O

Description

D0 − 17

Q0 − 7

Q9 − 16

I Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (D0 − 17) into

the FIFO’s memory. If MR is asserted at the rising edge of CKW, data is written into the FIFO’s

programming register. D8, 17 are ignored if the device is configured for parity generation.

O Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q0 − 7,

Q9 − 16) out of the FIFO’s memory. If MR is active at the rising edge of CKR, data is read from the

programming register.

Q8/PG1/PE1 O Function varies according to mode:

Q17/PG2/PE2

Parity disabled – same function as Q0 − 7 and Q9 − 16

Parity enabled, generation – parity generation bit (PGx)

Parity enabled, check – Parity Error Flag (PEx)

ENW

I Enable Write: Enables the CKW input (for both non-program and program modes).

ENR

I Enable Read: Enables the CKR input (for both non-program and program modes).

CKW

I Write Clock: The rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost

Full, and Full flag states. When MR is asserted, CKW writes data into the program register.

CKR

I Read Clock: The rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and

Almost Empty flag states. When MR is asserted, CKR reads data out of the program register.

HF

O Half Full Flag: Synchronized to CKW.

E/F

O Empty or Full Flag: E is synchronized to CKR; F is synchronized to CKW.

PAFE/XO

O Dual-Mode Pin:

Not Cascaded – programmable Almost Full is synchronized to CKW; Programmable Almost Empty is

synchronized to CKR.

Cascaded – expansion out signal, connected to XI of next device.

XI

I Expansion-In Pin:

Not Cascaded – XI is tied to VSS.

Cascaded – expansion Input, connected to XO of previous device.

FL/RT

I First Load/Retransmit Pin:

Cascaded – the first device in the daisy chain will have FL tied to VSS; all other devices will have FL tied

to VCC (Figure 1).

Not Cascaded – tied to VCC.

Retransmit function is also available in standalone mode by strobing RT.

MR

I Master Reset: Resets device to empty condition.

Non-Programming Mode: Program register is reset to default condition of no parity and PAFE active at

16 or less locations from Full/Empty.

Programming Mode: Data present on D0 - 9,10, or 11 and D15-17 is written into the programmable register

on the rising edge of CKW. Program register contents appear on Q0 - 9,10, or 11 and Q15-17 after the rising

edge of CKR.

OE

I Output Enable for Q0 − 7, Q9 − 16, Q8/PG1/PE1 and Q17/PG2/PE2 pins.

Document #: 38-06003 Rev. *A

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