CY7C1399-20VI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1399-20VI Datasheet PDF : 8 Pages
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CY7C1399
Switching Characteristics Over the Operating Range[5]
7C1399–12 7C1399–15 7C1399–20 7C1399–25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max.
READ CYCLE
tRC
Read Cycle Time
12
15
20
25
tAA
Address to Data Valid
12
15
20
25
tOHA
Data Hold from Address Change 3
3
3
3
tACE
CE LOW to Data Valid
12
15
20
25
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
5
6
7
8
0
0
0
0
5
6
6
7
3
3
3
3
6
7
7
8
tPU
CE LOW to Power-Up
0
0
0
0
tPD
CE HIGH to Power-Down
WRITE CYCLE[8, 9]
12
15
20
25
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[8]
WE HIGH to Low Z[6]
12
15
20
25
8
10
12
15
8
10
12
15
0
0
0
0
0
0
0
0
8
10
12
15
7
8
10
11
0
0
0
0
7
7
7
7
3
3
3
3
7C1399–35
Min. Max.
35
35
3
35
10
0
7
3
8
0
35
35
20
20
0
0
20
12
0
7
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min.
Max.
Unit
VDR
VCC for Data Retention
2.0
V
ICCDR
tCDR[4]
Data Retention Current
Chip Deselect to Data
Retention Time
VCC = VDR = 2.0V,
L
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
200
µA
20
µA
0
ns
tR[4]
Operation Recovery Time
tRC
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and capacitance CL = 30 pF.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD .
4
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