CY7C4261-15JC(2003) Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
производитель
CY7C4261-15JC Datasheet PDF : 18 Pages
| |||
Switching Waveforms (continued)
Reset Timing[16]
tRS
RS
REN1,
REN2
tRSS
tRSS
WEN1
WEN2/LD [18]
tRSS
EF,PAE
FF,PAF
Q0 - Q8
tRSF
tRSF
tRSF
First Data Word Latency after Reset with Read and Write
WCLK
tDS
D0 –D8
D0(FIRST VALID WRITE)
D1
WEN1
tENS
tFRL [19]
WEN2
(if applicable)
RCLK
EF
REN1,
REN2
tSKEW1
tREF
tRSR
tRSR
tRSR
D2
tA[20]
CY7C4261
CY7C4271
OE=1 [17]
OE=0
D3
D4
tA
Q0 –Q8
OE
tOLZ
tOE
D0
D1
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the
programmable flag offset registers.
19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06015 Rev. *B
Page 9 of 18
Share Link: 