CY7C4261-15JC(2003) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C4261-15JC Datasheet PDF : 18 Pages
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CY7C4261
CY7C4271
Switching Characteristics Over the Operating Range
7C4261/71−10 7C4261/71−15 7C4261/71−25 7C4261/71− 35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tRSF
tOLZ
tOE
tOHZ
tWFF
tREF
tPAF
tPAE
tSKEW1
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width[12]
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low Z[13]
Output Enable to Output Valid
Output Enable to Output in High Z[13]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
100
66.7
40
28.6 MHz
2
8
2 10 2 15 2 20 ns
10
15
25
35
ns
4.5
6
10
14
ns
4.5
6
10
14
ns
3
4
6
7
ns
0.5
1
1
2
ns
3
4
6
7
ns
0.5
1
1
2
ns
10
15
25
35
ns
8
10
15
20
ns
8
10
15
20
ns
10
15
25
35 ns
0
0
0
0
ns
3
7
3
8
3 12 3 15 ns
3
7
3
8
3 12 3 15 ns
8
10
15
20 ns
8
10
15
20 ns
8
10
15
20 ns
8
10
15
20 ns
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write Clock 10
15
18
20
ns
for Almost-Empty Flag and Almost-Full Flag
Notes:
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.
Document #: 38-06015 Rev. *B
Page 7 of 18
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