CY7C265-50DMB Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C265-50DMB

8K x 8 Registered PROM

Cypress Semiconductor 

CY7C265

Switching Waveform

ADDRESS

SYNCHRONOUS

ENABLE

(PROGRAMMABLE)

tSES

CLOCK

tAS

tHES

tPWC

OUTPUT

tDI

ASYNCHRONOUS INIT

(PROGRAMMABLE)

ASYNCHRONOUS

ENABLE

VALID DATA

tPWI

tRI

tHZC

tAH

tCOS

tCO

tHZE

tDOE

Erasure Characteristics

Wavelengths of light less than 4000 angstroms begin to erase

the 7C265 in the windowed package. For this reason, an

opaque label should be placed over the window if the PROM

is exposed to sunlight or fluorescent lighting for extended

periods of time.

The recommended dose of ultraviolet light for erasure is a

wavelength of 2537 angstroms for a minimum dose (UV

intensity • exposure time) of 25 Wsec/cm2. For an ultraviolet

lamp with a 12 mW/cm2 power rating the exposure time would

be approximately 45 minutes. The 7C265 needs to be within

one inch of the lamp during erasure. Permanent damage may

result if the PROM is exposed to high-intensity UV light for an

extended period of time. 7258 Wsec/cm2 is the recommended

maximum dosage.

Bit Map Data

Programmer Address (Hex.)

Decimal

Hex

0

.

.

8191

8192

8193

0

.

.

1FFF

2000

2001

RAM Data

Contents

Data

.

.

Data

INIT Byte

Control Byte

Control Byte

00 Asynchronous output enable (default condition)

01 Synchronous output enable

02 Asynchronous initialize

Programming Modes

The 7C265 offers a limited selection of programmed architec-

tures. Programming these features should be done with a

single 10-ms-wide pulse in place of the intelligent algorithm,

mainly because these features are verified operationally, not

with the VFY pin. Architecture programming is implemented by

applying the supervoltage to two additional pins during

programming. In programming the 7C265 architecture, VPP is

applied to pins 3, 9, and 22. The choice of a particular mode

depends on the states of the other pins during programming,

so it is important that the condition of the other pins be met as

set forth in the mode table. The considerations that apply with

respect to power-up and power-down during intelligent

programming also apply during architecture programming.

Once the supervoltages have been established and the

correct logic states exist on the other device pins,

programming may begin. Programming is accomplished by

pulling PGM from HIGH to LOW and then back to HIGH with

a pulse width equal to 10 ms.

Document #: 38-04012 Rev. *A

Page 5 of 11

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