CY7C197BN(2011) Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание

производитель

CY7C197BN
(Rev.:2011)

256-Kb (256 K × 1) Static RAM

Cypress Semiconductor 

Timing Waveforms (continued)

Read Cycle No. 2 [11, 12, 13]

tRC

Address

CY7C197BN

CE

tACE

tLZCE

tHZCE

Data Out

High Z

Data Valid

ICC

Vcc Supply Current ISB

tPU

50%

Write Cycle No. 1 (WE Controlled) [11, 14]

Address

CE

tSA

WE

Data In

Data Out

Data

Undefined

tWC

tSCE

tAW

tHA

tPWE

tHZWE

tSD

tHD

Data

Valid

tLZWE

High Impedance

High Z

tPD

50%

Notes

11. Tested initially and after any design or process change that may affect these parameters.

12. WE is HIGH in read cycle.

13. Address valid prior to or coincident with CE transition LOW.

14. The minimum write cycle time is the sum of tHZWE and tSD.

Document #: 001-06447 Rev. *C

Page 7 of 13

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