CY7C1512-70 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1512-70 Datasheet PDF : 8 Pages
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PRELIMINARY
Switching Characteristics[3, 6] Over the Operating Range (continued)
Parameter
Description
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[7, 8]
CE1 LOW to Low Z, CE2 HIGH to Low Z[8]
CE1 HIGH to High Z, CE2 LOW to High Z[7, 8]
tPU
CE1 LOW to Power-Up, CE2 HIGH to Power-Up
tPD
CE1 HIGH to Power-Down, CE2 LOW to Power-Down
WRITE CYCLE[9]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE1 LOW to Write End, CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[8]
WE LOW to High Z[7, 8]
Switching Waveforms
Read Cycle No. 1 [10, 11]
tRC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
11. WE is HIGH for read cycle.
CY7C1512
7C1512-35
Min. Min.
7C1512-70
Min. Min. Unit
35
70
ns
35
70
ns
5
5
ns
35
70
ns
15
15
ns
0
0
ns
15
15
ns
5
5
ns
15
15
ns
0
0
ns
35
70
ns
35
70
ns
25
60
ns
25
60
ns
0
0
ns
0
0
ns
25
60
ns
20
55
ns
0
0
ns
5
5
ns
15
15
ns
DATA VALID
1512-5
4
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