CY7C1361C-133AJXC(2006) Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание

производитель

CY7C1361C-133AJXC
(Rev.:2006)

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Cypress Semiconductor 

CY7C1361C

CY7C1363C

Pin Definitions (continued)

Name

VSS

VSSQ

TDO

TDI

TMS

TCK

NC

VSS/DNU

I/O

Description

Ground

Ground for the core of the device.

I/O Ground Ground for the I/O circuitry.

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

Synchronous JTAG feature is not being utilized, this pin should be left unconnected. This pin is not

available on TQFP packages.

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

Synchronous feature is not being utilized, this pin can be left floating or connected to VDD through a pull

up resistor. This pin is not available on TQFP packages.

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

Synchronous feature is not being utilized, this pin can be disconnected or connected to VDD. This pin

is not available on TQFP packages.

JTAG-

Clock

–

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must

be connected to VSS. This pin is not available on TQFP packages.

No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M

and 1G are address expansion pins and are not internally connected to the die.

Ground/DNU This pin can be connected to Ground or should be left floating.

Document #: 38-05541 Rev. *F

Page 8 of 31

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