CY7C1361B Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
производитель
CY7C1361B Datasheet PDF : 34 Pages
| |||
CY7C1361B
CY7C1363B
CY7C1363B: Pin Definitions (continued)
TQFP
TQFP
BGA
fBGA
(3-Chip
(2-Chip (2-Chip (3-Chip
Name
Enable)
Enable) Enable) Enable)
I/O
Description
ADSC
85
85
B4
A8
Input-
Address Strobe from Controller,
Synchronous sampled on the rising edge of CLK,
active LOW. When asserted LOW,
addresses presented to the device are
captured in the address registers. A[1:0] are
also loaded into the burst counter. When
ADSP and ADSC are both asserted, only
ADSP is recognized.
ZZ
64
64
T7
H11
Input-
ZZ “sleep” Input, active HIGH. When
Asynchronous asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
DQs
58,59,62,63, 58,59,62,63, P7,K7,G7, J10,K10,
I/O-
Bidirectional Data I/O lines. As inputs,
68,69,72,73, 68,69,72,73, E7,F6,H6, L10,M10, Synchronous they feed into an on-chip data register that
8,9,12,13, 8,9,12,13, L6,N6,D1, D11,E11,
is triggered by the rising edge of CLK. As
18,19,22,23 18,19,22,23 H1,L1,N1, F11,G11,J1,
outputs, they deliver the data contained in
E2,G2,K2, K1,L1,M1,
the memory location specified by the
M2
D2,E2,F2,
addresses presented during the previous
G2
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:B] are placed
in a three-state condition.The outputs are
automatically three-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
DQP[A:B]
74,24
MODE
31
74,24
31
D6,P2
R3
C11,N1
R1
I/O-
Synchronous
Input-Static
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to
DQs. During write sequences, DQP[A:B] is
controlled by BW[A:B] correspondingly.
Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
VDD
15,41,65,91 15,41,65,91 C4,J2,J4, D4,D8,E4, Power Supply Power supply inputs to the core of the
J6,R4 E8,F4,F8,
device.
G4,G8,
H4,H8,J4,
J8,K4,K8,
L4,L8,M4,
M8
VDDQ
4,11,20,27, 4,11,20,27, A1,A7,F1,
54,61,70,77 54,61,70,77 F7,J1,J7,
M1,M7,U1
,U7
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
I/O Power Power supply for the I/O circuitry.
Supply
Document #: 38-05302 Rev. *B
Page 11 of 34
Share Link: 