CY7C1359A-100AC Просмотр технического описания (PDF) - Cypress Semiconductor
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производитель
CY7C1359A-100AC Datasheet PDF : 24 Pages
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CY7C1359A/GVT71256T18
Pin Descriptions (continued)
BGA Pins
6P
TQFP Pins
51
Name
MOE
7P, 6N, 6L, 7K,
6H, 7G, 6F, 7E,
6D, 1D, 2E, 2G,
1H, 2K, 1L, 2M,
1N, 2P
58, 59, 62, 63, 68,
69, 72, 73, 74, 8,
9, 12, 13, 18, 19,
22, 23, 24
5U
42
2U
38
3U
39
4U
43
4C, 2J, 4J, 6J, 4R 15, 41,65, 91
3D, 5D, 3E, 5E,
3F, 5F, 5G, 3H,
5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N,
3P, 5P
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
1A, 7A, 1F, 7F, 1J, 4, 11, 20, 27, 54,
7J, 1M, 7M, 1U,
61, 70, 77
7U
1B, 7B, 1C, 7C,
2D, 4D, 7D, 1E,
6E, 2F, 1G, 6G,
2H, 7H, 3J, 5J,
1K, 6K, 2L, 4L,
7L, 2N, 1P, 1R,
5R, 7R, 1T, 4T, 6U
1-3, 6, 7, 14, 16,
25, 28-30, 56, 57,
66, 75, 78, 79, 95,
96
DQ1–
DQ18
TDO
TMS
TDI
TCK
VCC
VSS
VCCQ
NC
Type
Input
Input/
Output
Description
Match Output Enable: This active LOW asynchronous input
enables the MATCH output drivers.
Data Inputs/Outputs: Input data must meet setup and hold
times around the rising edge of CLK.
Output
Input
IEEE 1149.1 test output. LVTTL-level output.
IEEE 1149.1 test inputs. LVTTL-level inputs.
Supply
Ground
Power Supply: +3.3V –5% and +10%
Ground: GND
I/O Supply Output Buffer Supply: +2.5V (from 2.375V to VCC)
-
No Connect: These signals are not internally connected.
Burst Address Table (MODE = NC/VCC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A00
A...A01
A...A10
Partial Truth Table for MATCH[2, 3, 4, 5, 6]
Operation
E
WE
DEN
MOE
OE
MATCH
DQ
READ Cycle
L
H
X
X
L
-
Q
WRITE Cycle
L
L
L
X
H
-
D
Fill WRITE Cycle
L
L
H
X
H
-
High-Z
COMPARE Cycle
L
H
L
L
H
Output
D
Deselected Cycle (MATCH Out)
H
X
X
L
X
H
High-Z
Deselected Cycle
H
X
X
H
X
High-Z
High-Z
Notes:
2. X means “don’t care.” H means logic HIGH. L means logic LOW. It is assumed in this table that ADSP is HIGH and ADSC is LOW.
3. E=L is defined as CE=LOW and CE2=LOW and CE2=HIGH. E =H is defined as CE=HIGH or CE2=HIGH or CE2=LOW. WE is defined as [BWE + WEL*WEH]*GW.
4. All inputs except OE and MOE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
Document #: 38-05120 Rev. **
Page 5 of 24
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