CY7C1359A-100AC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1359A-100AC Datasheet PDF : 24 Pages
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CY7C1359A/GVT71256T18
Selection
Circuitry
TDI
0
Bypass Register
210
Instruction Register
Selection
Circuitry
TDO
31 30 29 . . 2 1 0
Identification Register
x.
. . . 210
Boundary Scan Register [14]
TDI
TAP Controller
TDI
Figure 2. TAP Controller Block Diagram
TAP DC Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted)
Parameter
Description
Test Conditions
Min.
Max.
Unit
VIH
Input High (Logic 1) Voltage[15, 16]
VIl
Input Low (Logic 0) Voltage[15, 16]
2.0
–0.3
VCC + 0.3
V
0.8
V
ILI
Input Leakage Current
0V < VIN < VCC
–5.0
5.0
µA
ILO
VOLC
VOHC
VOLT
VOHT
Output Leakage Current
LVCMOS Output Low Voltage[15, 17]
LVCMOS Output High Voltage[15, 17]
LVTTL Output Low Voltage[15]
LVTTL Output High Voltage[15]
Output disabled,
0V < VIN < VCCQ
IOLC = 100 µA
IOHC = 100 µA
IOLT = 8.0 mA
IOHT = 8.0 mA
–5.0
VCC – 0.2
2.4
5.0
µA
0.2
V
V
0.4
V
V
Notes:
14. X = 53 for this device.
15. All Voltage referenced to VSS (GND).
16. Overshoot: VIH(AC)<VCC+1.5V for t<tKHKH/2, Undershoot: VIL(AC)<–0.5V for t<tKHKH/2, Power-up: VIH<3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms.
During normal operation, VCCQ must not exceed VCC. Control input signals (such as GW, ADSC, etc.) may not have pulse widths less than tKHKL (min.).
17. This parameter is sampled.
Document #: 38-05120 Rev. **
Page 10 of 24
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