CY7C1347D-250 Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1347D-250

128K x 36 Synchronous-Pipelined Cache SRAM

Cypress Semiconductor 

TAP Timing and Test Conditions

TDO

Z0 = 50 Ω

50 Ω

20 pF

Vt = 1.5Vfor 3.3V VCCQ or

(a)

VCCQ/2 for 2.5V VCCQ

tTHTH

TEST CLOCK

(TCK)

TEST MODE SELECT

(TMS)

TEST DATA IN

(TDI)

tMVTH tTHMX

tDVTH tTHDX

TEST DATA OUT

(TDO)

Identification Register Definitions

Instruction Field

Revision Number (31:28)

Device Depth (27:23)

Device Width (22:18)

Reserved (17:12)

Cypress Jedec Id Code (11:1)

ID Register Presence Indicator (0)

128K x 36

XXXX

00111

00011

XXXXXX

00011100100

1

Scan Register Sizes

Register Name

Instruction

Bypass

ID

Boundary Scan

Bit Size (x36)

3

1

32

51

CY7C1347D

ALL INPUT PULSES

3.3V / 2.5V

VSS 1.5 ns

1.5V

1.5 ns

tTHTL

tTLTH

tTLQV

tTLQX

Description

Reserved for revision number.

Defines depth of words.

Defines width of bits.

Reserved for future use.

Allows unique identification of DEVICE vendor.

Indicates the presence of an ID register.

Document #: 38-05022 Rev. *D

Page 11 of 21

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