CY7C1340F-100AC Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1340F-100AC

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Cypress Semiconductor 

Switching Waveforms (continued)

Read/Write Timing[17, 19, 20]

tCYC

CLK

ADSP

tCH tCL

tADS tADH

ADSC

ADDRESS A1

tAS tAH

A2

BWE, BW[A:D]

tCES tCEH

CE

A3

A4

tWES tWEH

CY7C1340F

A5

A6

ADV

OE

Data In (D)

Data Out (Q)

tCO

tDS tDH

tOELZ

High-Z

D(A3)

tCLZ

tOEHZ

High-Z

Q(A1) Q(A2)

Back-to-Back READs

Single WRITE

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

BURST READ

DON’T CARE

UNDEFINED

Notes:

19. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

20. GW is HIGH.

D(A5) D(A6)

Back-to-Back

WRITEs

Document #: 38-05219 Rev. *A

Page 14 of 17

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