CY7C1325G Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1325G Datasheet PDF : 16 Pages
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Pin Configurations (continued)
119-Ball BGA Pinout
CY7C1325G
1
2
A
VDDQ
A
B NC/288M CE2
C NC/144M A
D
DQB
NC
E
NC
DQB
F
VDDQ
NC
G
NC
DQB
H
DQB
NC
J
VDDQ
VDD
K
NC
DQB
L
DQB
NC
M
VDDQ
DQB
N
DQB
NC
P
NC
DQPB
R
NC
A
T NC/72M A
U
VDDQ
NC
3
A
A
A
VSS
VSS
VSS
BWB
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
NC
4
ADSP
ADSC
VDD
NC
CE1
OE
ADV
GW
VDD
CLK
NC
BWE
A1
A0
VDD
NC/36M
NC
5
A
A
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
BWA
VSS
VSS
VSS
NC
A
NC
6
A
CE3
A
DQPA
NC
DQA
NC
DQA
VDD
NC
DQA
NC
DQA
NC
A
A
NC
7
VDDQ
NC/576M
NC/1G
NC
DQA
VDDQ
DQA
NC
VDDQ
DQA
NC
VDDQ
NC
DQA
NC
ZZ
VDDQ
Pin Definitions
Name
A0, A1, A
BWA,BWB
GW
BWE
CLK
CE1
CE2
CE3
OE
I/O
Description
Input-
Address Inputs used to select one of the 256K address locations. Sampled at the rising edge
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
feed the 2-bit counter.
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address
is loaded.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address
is loaded.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Document #: 38-05518 Rev. *D
Page 3 of 16
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