CY7C1316AV18 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1316AV18 Datasheet PDF : 20 Pages
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CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Pin Configurations (continued)
CY7C1320AV18 (512K × 36)—11 × 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
A
CQ VSS/144M NC/36M R/W BWS2
K
BWS1
LD
A VSS/72M CQ
B
NC DQ27 DQ18
A
BWS3
K
BWS0
A
NC
NC
DQ8
C
NC
NC
DQ28
VSS
A
A0
A
VSS
NC DQ17 DQ7
D
NC
DQ29 DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC DQ16
E
NC
NC
DQ20 VDDQ
VSS
VSS
VSS
VDDQ
NC DQ15 DQ6
F
NC
DQ30 DQ21 VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31 DQ22 VDDQ
VDD
VSS
VDD
VDDQ
NC
NC DQ14
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32 VDDQ
VDD
VSS
VDD
VDDQ
NC DQ13 DQ4
K
NC
NC
DQ23 VDDQ
VDD
VSS
VDD
VDDQ
NC DQ12 DQ3
L
NC
DQ33 DQ24 VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
NC DQ11 DQ1
N
NC
DQ35 DQ25
VSS
A
A
A
VSS
NC
NC DQ10
P
NC
NC DQ26
A
A
C
A
A
NC
DQ9 DQ0
R
TDO TCK
A
A
A
C
A
A
A
TMS
TDI
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
LD
Input/Output- Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid
Synchronous Write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When read access is deselected, Q[x:0] are automatically three-stated.
CY7C1316AV18 − DQ[7:0]
CY7C1318AV18 − DQ[17:0]
CY7C1320AV18 − DQ[35:0]
Input- Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined.
Synchronous This definition includes address and Read/Write direction. All transactions operate on a burst of
2 data.
BWS0, BWS1, Input- Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
BWS2, BWS3 Synchronous during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1316AV18 − BWS0 controls D[3:0] and BWS1 controls D[7:4].
CY7C1318AV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1320AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A, A0
Input- Address Inputs. These address inputs are multiplexed for both Read and Write operations.
Synchronous Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1316AV18, a
single 1M x 18 array for CY7C1318AV18, and a single array of 512K x 36 for CY7C1320AV18.
CY7C1316AV18 – Since the least significant bit of the address internally is a “0,” only 20 external
address inputs are needed to access the entire memory array.
CY7C1318AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 20 address inputs are needed to access the entire memory array.
CY7C1320AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 19 address inputs are needed to access the entire memory array. All the address inputs
are ignored when the appropriate port is deselected.
Document #: 38-05499 Rev. *B
Page 4 of 20
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