CY7C1297H-133AXC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1297H-133AXC Datasheet PDF : 15 Pages
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Switching Characteristics Over the Operating Range [10, 11]
Parameter
tPOWER
Clock
Description
VDD(Typical) to the First Access[12]
tCYC
Clock Cycle Time
tCH
Clock HIGH
tCL
Clock LOW
Output Times
tCDV
Data Output Valid after CLK Rise
tDOH
tCLZ
tCHZ
Data Output Hold after CLK Rise
Clock to Low-Z[13, 14, 15]
Clock to High-Z[13, 14, 15]
tOEV
tOELZ
tOEHZ
OE LOW to Output Valid
OE LOW to Output Low-Z[13, 14, 15]
OE HIGH to Output High-Z[13, 14, 15]
Set-up Times
tAS
tADS
tADVS
tWES
tDS
tCES
Hold Times
Address Set-up before CLK Rise
ADSP, ADSC Set-up before CLK Rise
ADV Set-up before CLK Rise
GW, BWE, BW[A:B] Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-up
tAH
tADH
tWEH
tADVH
tDH
tCEH
Address Hold after CLK Rise
ADSP, ADSC Hold after CLK Rise
GW, BWE, BW[A:B] Hold after CLK Rise
ADV Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
CY7C1297H
133 MHz
100 MHz
Min. Max. Min. Max. Unit
1
1
ms
7.5
10.0
ns
2.5
4.0
ns
2.5
4.0
ns
6.5
8.0
ns
2.0
2.0
ns
0
0
ns
3.5
3.5
ns
3.5
3.5
ns
0
0
ns
3.5
3.5
ns
1.5
2.0
ns
1.5
2.0
ns
1.5
2.0
ns
1.5
2.0
ns
1.5
2.0
ns
1.5
2.0
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
Notes:
10. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation
can be initiated.
13. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
Document #: 38-05669 Rev. *B
Page 9 of 15
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