CY7C1297H-133AXI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1297H-133AXI Datasheet PDF : 15 Pages
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CY7C1297H
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Truth Table[2, 3, 4, 5, 6]
Test Conditions
Min.
Max.
Unit
ZZ > VDD – 0.2V
40
mA
ZZ > VDD – 0.2V
2tCYC
ns
ZZ < 0.2V
2tCYC
ns
This parameter is sampled
2tCYC
ns
This parameter is sampled
0
ns
Cycle Description
Deselected Cycle,
Power-down
Address Used CE1 CE2 CE3 ZZ ADSP
None
H X XL X
Deselected Cycle,
Power-down
None
L L XL L
Deselected Cycle,
Power-down
None
L X HL L
Deselected Cycle,
Power-down
None
L L XL H
Deselected Cycle,
Power-down
None
X X XL H
Sleep Mode, Power-down
None
X X XH X
Read Cycle, Begin Burst
External
L H LL L
Read Cycle, Begin Burst
External
L H LL L
Write Cycle, Begin Burst
External
L H LL H
Read Cycle, Begin Burst
External
L H LL H
Read Cycle, Begin Burst
External
L H LL H
Read Cycle, Continue Burst
Next
X X XL H
Read Cycle, Continue Burst
Next
X X XL H
Read Cycle, Continue Burst
Next
H X XL X
Read Cycle, Continue Burst
Next
H X XL X
Write Cycle, Continue Burst
Next
X X XL H
Write Cycle, Continue Burst
Next
H X XL X
Read Cycle, Suspend Burst Current
X X XL H
Read Cycle, Suspend Burst Current
X X XL H
Read Cycle, Suspend Burst Current
H X XL X
Read Cycle, Suspend Burst Current
H X XL X
Write Cycle, Suspend Burst
Current
X X XL H
Write Cycle, Suspend Burst
Current
H X XL X
ADSC
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE OE
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
H
L
X
H
L
H
H
H
L
H
H
H
L
H
H
L
X
L
X
H
L
H
H
H
L
H
H
L
X
L
X
CLK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Q
Tri-State
D
Q
Tri-State
Q
Tri-State
Q
Tri-State
D
D
Q
Tri-State
Q
Tri-State
D
D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA, BWB),
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05669 Rev. *B
Page 5 of 15
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