CY7C1297H-133AXI Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1297H-133AXI

1-Mbit (64K x 18) Flow-Through Sync SRAM

Cypress Semiconductor 

Timing Diagrams

Read Cycle Timing[16]

CY7C1297H

CLK

ADSP

ADSC

ADDRESS

GW, BWE,BW

[A:B]

CE

ADV

OE

Data Out (Q)

tCYC

t CH t CL

tADS tADH

tADS tADH

tAS tAH

A1

A2

t WES tWEH

tCES tCEH

t

ADVS

tADVH

Deselect Cycle

ADV suspends burst.

tOEV

High-Z

tCLZ

tCDV

tOEHZ

Q(A1)

Single READ

tOELZ

tCDV

tDOH

Q(A2) Q(A2 + 1)

Q(A2 + 2)

DON’T CARE

BURST

READ

UNDEFINED

Q(A2 + 3)

tCHZ

Q(A2) Q(A2 + 1) Q(A2 + 2)

Burst wraps around

to its initial state

Note:

16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05669 Rev. *B

Page 10 of 15

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