UPD705102 Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD705102

V832™ 32-BIT MICROPROCESSOR

NEC => Renesas Technology 

µPD705102

2. INTERNAL UNITS

(1) Bus control unit (BCU)

Controls the address bus, data bus, and control bus pins. The major functions of BCU are as follows:

(a) Bus arbitration

Arbitrates the bus mastership among bus masters (CPU, SDRAMC, DMAC, and external bus masters). The

bus mastership can be changed after completion of the bus cycle under execution, and in an idle state.

(b) Wait control

Controls eight areas in the 16-Mbyte space corresponding to eight chip select signals (CS0 through CS7).

Generates chip select signals, controls wait states, and selects the type of bus cycle.

(c) SDRAM controller

Generates commands and controls access to SDRAM. CAS latency is 2 only.

(d) ROM controller

Accessing ROM with page access function is supported. The bus cycle immediately before and addresses

are compared, and wait states are controlled in the normal access (off-page) or page access (on-page)

modes. A page width of 8 bytes to 16 bytes can be supported.

(2) Interrupt controller (ICU)

Services maskable interrupt requests (INTP00 through INTP03, and INTP10 through INTP13) from internal

peripheral hardware and external sources. The priorities of these interrupt requests can be specified in units of

four groups, and edge-triggered or level-triggered interrupts can be nested.

(3) DMA controller (DMAC)

Transfers data between memory and I/O in place of CPU. The transfer type is 2-cycle transfer. Two transfer

modes, single transfer and demand transfer, are available.

(4) Serial interface (UART/CSI/BRG)

One asynchronous serial interface (UART) channel and one clocked serial interface (CSI) channel is provided.

As the serial clock source, the output of the baud rate generator (BRG) and the bus clock can be selected.

(5) Real-time pulse unit (RPU)

Provides timer/counter functions. The on-chip 16-bit timer/event counter and 16-bit interval timer can be used

to calculate pulse intervals and frequencies, and to output programmable pulses.

(6) Clock generator (CG)

A frequency six or eight times higher than that of the resonator connected to the X1 and X2 pins is supplied as

the operating clock of the CPU. In addition, both a bus clock, which functions as the operating clock of the

peripheral units, and SDCLKOUT, which functions as an operating clock, are supplied from the CLKOUT pin. An

external clock can be also input instead of connecting a resonator.

For reducing the power consumption, the function switching the frequencies of the CPU clock and bus clock with

power management control (PMC) is provided.

Data Sheet U13675EJ2V1DS00

9

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