CY7C1061AV33-12ZXI Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание

производитель

CY7C1061AV33-12ZXI

16-Mbit (1M x 16) Static RAM

Cypress Semiconductor 

CY7C1061AV33

Data Retention Waveform

VCC

3.0V

tCDR

CE

DATA RETENTION MODE

VDR > 2V

3.0V

tR

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled) [12, 13]

tRRCC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

DATA VALID

Read Cycle No. 2 (OE Controlled) [13, 14]

ADDRESS

tRC

CE1

CE2

BHE/BLE

OE

tACE

tLZBE

tDBE

DATA OUT

VCC

SUPPLY

CURRENT

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

Notes

12. Device is continuously selected. OE, CE, BHE or BHE, or both = VIL. CE2 = VIH.

13. WE is HIGH for Read cycle.

14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

Document #: 38-05256 Rev. *G

DATA VALID

tPD

tHZCE

tHZBE

tHZOE

HIGH

IMPEDANCE

ICC

50%

ISB

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