CY7C1021CV26 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1021CV26 Datasheet PDF : 16 Pages
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Switching Characteristics (continued)
Over the Operating Range
Parameter [6]
Write Cycle[10]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Write cycle time
CE LOW to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
WE pulse width
Data set-up to write end
Data hold from write end
WE HIGH to low Z[11]
WE LOW to high Z[11, 12]
Byte enable to end of write
Description
CY7C1021CV26
-15
Unit
Min
Max
15
–
ns
10
–
ns
10
–
ns
0
–
ns
0
–
ns
10
–
ns
8
–
ns
0
–
ns
3
–
ns
–
7
ns
9
–
ns
Notes
10. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and
the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
12. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 3 on page 6. Transition is measured 500 mV from steady-state voltage.
Document Number: 38-05589 Rev. *F
Page 7 of 16
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