CY7C037AV-20AXC(2011) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C037AV-20AXC Datasheet PDF : 22 Pages
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CY7C027V/027AV/028V
CY7C037AV/038V
Switching Characteristics Over the Operating Range[12](continued)
Parameter
Description
tHD
Data hold from write end
tHZWE[17, 18]
R/W LOW to High Z
tLZWE[17, 18]
R/W HIGH to Low Z
tWDD[21]
Write pulse to data delay
tDDD[21]
Write data valid to read data valid
Busy Timing[19]
tBLA
BUSY LOW from address match
tBHA
BUSY HIGH from address mismatch
tBLC
BUSY LOW from CE LOW
tBHC
BUSY HIGH from CE HIGH
tPS
Port setup for priority
tWB
R/W HIGH after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH (Slave)
tBDD[21]
BUSY HIGH to data valid
Interrupt Timing[19]
tINS
INT set time
tINR
INT reset time
Semaphore Timing
tSOP
tSWRD
tSPS
tSAA
SEM flag update pulse (OE or SEM)
SEM flag write to read time
SEM flag contention window
SEM address access time
CY7C027V/027AV/028V/
CY7C037AV/CY7C038V
-15
-20
-25
Min Max Min Max Min Max
0
–
0
–
0
–
–
10
–
12
–
15
3
–
3
–
3
–
–
30
–
40
–
50
–
25
–
30
–
35
–
15
–
20
–
20
–
15
–
20
–
20
–
15
–
20
–
20
–
15
–
16
–
17
5
–
5
–
5
–
0
–
0
–
0
–
13
–
15
–
17
–
–
15
–
20
–
25
–
15
–
20
–
20
–
15
–
20
–
20
10
–
10
–
12
–
5
–
5
–
5
–
5
–
5
–
5
–
–
15
–
20
–
25
Data Retention Mode
Timing
The CY7C027V/027AV/028V and CY7037AV/038V are de-
signed with battery backup in mind. Data retention voltage and
supply current are guaranteed over temperature. The following
rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention, within
VCC to VCC – 0.2 V
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power up and power down transitions
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0 V)
Data Retention Mode
VCC
3.0 V
VCC 2.0 V
3.0 V
tRC
CE
VCC to VCC – 0.2 V
VIH
Parameter
Test Conditions[22] Max
ICCDR1
At VCCDR = 2 V
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
A
Notes
17. Test conditions used are Load 2
18. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer
to Figure 11.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 waveform.
20. Test conditions used are Load 1.
21. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
22. CE = VCC, Vin = GND to VCC, TA = 25 C. This parameter is guaranteed but not tested.
Document #: 38-06078 Rev. *E
Page 9 of 22
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